In designing a phase-locked loophol...

In designing a phase-locked loophole for use on several HP ASICs the digital portion of an existing phase-locked loophole was transferred to a behavioral VHDL description and synthesized. A behavioral protoplast was written for the analog section to allow the ASIC designers to haste system simulations. A new leakage ordeal was developed that has been extremely effective in screening out proces deficiencys in the filter of the original design.

This paper describes the design and integration proces for a phase-locked aperture that is being used onward several current HP ASICs (application-specific integrated circuits). The design is based upon the phase-locked loop for a previous ASIC, moreover several improvements were made. First, the digital portion of the phase-locked turn was transferred to a behavioral VHDL(*) description and synthesized. Reusability was a big consideration in writing the digest The portable nature of the VHDL digest enabled us to design several phase-locked crooks within a very short time. secondary a behavioral model was written for the analog section to allow the ASIC designers to hie system simulations. This model, when combined with the protoplast for the digital section, allows the designer to simulate the phase-locked link as it locks--it does not simply put out an ideal clock waveform. Finally, in a previous ASIC, a large resistor and capacitor in the bight filter were not adequately criterioned For the new phase-locked bend we developed a leakage experiment that has been very effective in screening on the outside process defects in the filter.

An analog phase-locked turn presents several challenges to designers in an all-digital design environment. near all-digital simulators, such as Verilog XL cannot set forth analog signals easily. System designers must either use a mixed-mode simulator to exhibit the analog portions of the phase-locked aperture or use a simplified pattern of the phase-locked loop. In ASIC production exhibition limitations of the production proof equipment must be taken into account. For example, an analog measurement may take a lengthy time to complete. Also, functional tester cannot measure oftenness so it is difficult to determine that the phase-locked bight is operating properly in production test

Previous Phase-Locked loophole Design

The previous phase-locked noose design appeared on an ASIC, where its intent was to accept an input clock (the video clock) and generate the scheme clock. The clock signal output from the phase-locked noose was modulated so that the output clock common occurrence alternated back and forth between sum of two units frequencies slightly above and below the target regularity clock frequency. This frequency modulation of the theory clock was required by the theory in which the previous design was used.

The block up diagram of the previous phase-locked turn is shown in Fig. 1 The loophole consists of an input reckoner (divide-by-M), a feedback counter (divide-by-N), a phase-frequency detector, a charge cross-examine and filter, a voltage-controlled oscillator (VCO) and other digital bridle logic. The input counter divides the input clock by means of either [N.sub.high] or [N.sub.low]. It bring into beings an output pulse (FREF) that is depressed for one clock cycle and high for the remaining time. The feedback contrary divides the VCO output according to [N.sub.high] or [N.sub.low] It exhibits an output pulse (FBAK) that is cheap for two clock cycles. The phase-frequency detector examines the relative phase of the rising zests of the FREF and FBAK signals and generates fruit of leguminous plantss on the UP and DOWN signal lines. The charge cross-question uses these pulses to adjust the check voltage for the VCO. The output signal is generated by way of dividing the VCO output clock at 4. The resulting phase-locked loophole output frequency is given by:

[Figure 1 ILLUSTRATION OMITTED]

(1) [fsubout] = 1/4 (N/M) [f.sub.i]

The repress block consists of logic that single outs one of the operating frequencies. A state machine in this stiffen controls the modulation between the upper and lower frequencies. In normal variety the control logic sets the phase-locked bend to the upper frequency when it is reset The aperture remains at the upper common occurrence until the control block receives a signal that indicates that the crook is locked. After this, the aperture alternates between the upper and lower frequencies. This is controll according to the N_SEL and M_SEL output of the modulator counter

There were sum of two units main problems with the integration of the phase-locked crook The first problem was that there was no design of the phase-locked loop in VHDL or Verilog that could be used for classification simulation. Therefore, no simulations were hie with the clock generated by dint of the phase-locked loop. All simulations were trip with an external clock, using a different chip modification This caused the design team to miss a serious bug in the design. When the quality pins were set to enable the phase-locked turn one block inside the chip was accidently risk into scan mode. This point to be solved [i]or[/i] settled was not caught until the first prototype parts were placed forward a board.

The second vexed question encountered with this phase-locked bend design was a high production line failure rate. The phase-locked turn tests were not catching all the defective parts. Analysis of the turn backed parts showed that the failures were caused by dint of defects in the resistor and capacitor in the crook filter, which caused excessive leakage, changing the filter characteristics. The production tester had no way to proof for this, so a fresh test had to be created. Here the lack of a serviceable simulation model for the phase-locked noose was a real handicap. The original trials for the phase-locked loop were debugg forward the tester. When trying gone out new tests, we had no way of simulating them to verify their correctness. Thus, it took sum of two units or three iterations before the exhibitions were correct.