The goals of the work quick in emer...

The goals of the work quick in emergenciesed in this paper were to estimate quantitatively the impact of interconnect technology parameters forward the performance of high-end microprocessors and to use this information to optimize the interconnect geometry within the constraints imposed by way of the process The 64-bit PA 8000 microprocessor was used as a criterion case.

For the past sum of two units decades the driving force for integrated circuits has been scaling of one as well as the other the devices and the interconnect. This has yielded faster and denser chips with always increasing functionality. Today's high-performance micro-processors have 4 to 5 million logic transistors[1,2,3] and operate in the frequent occurrence range of 200 to 250 MHz To stay upon the trend for CPU performance gains, the next-generation processors will likely have clock flourishs of 400 to 500 MHz and have up to 10 million transistors for the logic implementation.[4] The design and manufacture of arrangements that provide such performance will require careful attention to all proces device, and circuit issues.

In particular, the interconnect plan for the next-generation CPUs destitutions to sustain the burden of connecting 10 million transistors with 5 to 6 metal layers through a 2-cm die with a clock period of 2 to 2.5 n Because the interconnect scheme affects the manufacturing yield, reliability, performance, and design complexity of a CPU it cannot be optimized in isolation nevertheless rather must take into account all these aspects.

The goal of the work neared in this paper was duplicate First, we wanted a quantitative estimate of the impact of interconnect technology parameters in succession the performance of high-end microprocessors. secondary we wanted to use this information to optimize the interconnect geometry within the constraints imposed through the process. It is well-known that interconnect will become an increasingly significant factor in the design of that will be high-performance processors.[4,5] Therefore, it is important to benchmark the generally received technology with realistic process parameters and circuit designs. The detailed layout and extracted data for the HP PA 8000 microprocessor[1] provided an ideal testbed to perform one as well as the other of these tasks.

Two criteria were used for optimization: delay or rise time (they have self-same similar characteristics) and cross talk noise.[6,7] The optimization was performed simply for the global (block-to-block) routing consisting of metal layers 2 3 and 4 Because the longest signal wires are usually at this of the same height of routing, optimizing these layers has the mostly direct impact on system performance. For optimization, we solely considered nets that had marginal timing based forward the expected performance target for the processor.

Optimization Methodology

Our optimization approach is as follows:

1 Determine the timing-critical toils using a global static timing simulator.

2 From this fix of nets select a sample that has significant global interconnect.

3 Extract the driver sizes and wire fulnesss for this inter-connect-dominated subset of the global nets

4 For these global interconnect dominated unadulterateds determine the sensitivity to all interconnect parameters: metal thickness, width, and space and dielectric thickness.

5 For pair of the most sensitive parameters perform two-dimensional optimization to determine the best design point for each metal layer considered (metal 2 3 and 4)

The total wire capacitance and cros talk are calculated assuming a compact geometry with neighboring lines within the plane of the signal line and soil planes above and below, as shown in Fig. 1 The wire capacitance is obtained using the field solver RAPHAEL in 2D and the cros talk and delay are obtained from SPICE simulations using the coupling and total capacitances generated from RAPHAEL. The cross-talk noise and delay were simulated in worst-case situations. For delay this means that the neighboring lines were switching simultaneously in the direction opposite to the signal line, and for cros talk the victim line was quiescent while the neighboring lines switched simultaneously in the same direction.

[Figure 1 ILLUSTRATION OMITTED]

Results

Fig. 2 point out tos the distribution of metal longitudinal dimensionss among the nets that failed the timing criterion at the target common occurrence A significant number of critical toils have long metal 2 and metal 4 lines while metal 3 is usually to a great degree shorter. This is, of course, a direct issue of the orthogonal channel routing scheme used by the agency of the HP-proprietary automatic router, PA-ROUTE. The other salient feature of Fig. 2 is the large number of traps that have 5 to 6 mm of metal 2 Similarly, there is a secondary peak of 4 to 5 mm for metal 4 Thus, an obvious target for optimization is wires that have this typical protracted length. We did not rare the longest wires for optimization because they were not typical.

[Figure 2 ILLUSTRATION OMITTED]

The drivers for all of the clears studied were approximately 44 [micro] m wide ([Wsubn] = width of e-channel transistor = 44 [micro] m; [Wsubp] = width of p-channel transistor = 2[Wsubn]) The drivers were large enough that the delays and rise times were determined primarily from the interconnect and not the driver size.