This combination of a digital oscil...

This combination of a digital oscilloscope and a logic timing analyzer provides powerful cross-domain triggering capabilities for capturing signals in mixed-signal environments MegaZoom technology consisting of advanced acquisition techniques and dedicated signal processing, maintains display responsiveness while making optimal use of knotty sample memory.

The design of the HP 54645A/D oscilloscopes introduced in the article in succession page 6 began with the HP 54645A, envisioned as a performance upgrade to the HP 54600 Series oscilloscopes.[1] These oscilloscopes, introduced in 1991 have an almost analog expect and feel. Their three-processor design yields unprecedent display update rate and responsiveness at an affordable price. The major design goal for the HP 54645A was to improve the sample rate performance at an order of magnitude while maintaining the responsiveness and display update rate of the existing HP 54600 Series products

Ultimately, brace new products were created: the HP 54645A two-channel oscilloscope and the HP 54645D mixed-signal oscilloscope. The mixed-signal oscilloscope is a strange product category that adds 16 logic timing analyzer inputs to the sum of two units channels of oscilloscope input. In addition to displaying all 16 logic channels, the HP 54645D provides advanced logic triggering functions onward patterns that can span all 18 channels.

The HP 54645A and 54645D were designed concurrently We made each effort to have the oscilloscope-only production (the HP54645A) be simply the combination produce (the HP54645D), with an external trigger circuit substituted for the digital channel subsystem equable the firmware ROM in the sum of two units products is identical.

Architecture

We started the design by dint of modifying the architecture. A simplified brace diagram of an HP 54600 Series oscilloscope is shown in Fig. 1 sum of two units ICs form the core of the system: the acquisition processor and the display processor. The display a whole was left alone and simply the acquisition circuitry was redesigned. We kept the same display, the same package, the same analog brass end, and the same army 68000 processor.

[Figure 1 ILLUSTRATION OMITTED]

In the original HP 54600 design, the acquisition processor IC was responsible for taking the digitized samples from the analog-to-digital converter (ADC) and placing them into an external memory as time-ordered pairs, which the display processor IC placed onward the CRT display. More specifically, the acquisition tasks include:

* Generation of the sample clock for the ADCs and controlling the decimation of the sample clock and dither algorithms for use at slower time base settings.

*Peak detection of the ADC data. This blockade calculates the minimum and maximum values of the sampled data.

* Intermediate storage of the ADC data (or minimum/maximum pairs if the peak-detector is used) into an internal circular 2K-sample memory. This memory, known as the capture RAM, shut ups the data until the trigger point is calculated.

* Accepting the analog trigger from united of the channels and measuring the time between the trigger and the same of the sample clock edges

* After the trigger is establish unloading the data from the capture RAM into an external RAM known as the waveform RAM. For each sample value, a corresponding x-axis (time) value is calculated.

All of these tasks were integrated into single chip for the HP 54600 oscilloscopes. For the of recent origin products, we divided the above functions into separate, discrete composings as shown in Fig. 2

[Figure 2 ILLUSTRATION OMITTED]

Clock Generation. often of the difficulty of the original one-IC design stemm from unwanted coupling between the sample clock and the trigger clock In a digital oscilloscope, in the same state [i]or[/i] condition coupling can severely corrupt the time base fidelity, causing time-axis nonlinearities ("bowing in time"), time-axis discontinuities, and sample bunching. In a higher-frequency instrument, the design of the clocking and trigger bodys would have been all the more difficult. Consequently the of the present day products have a separate, dedicated bipolar IC for handling the clock generation and triggering.

Peak Detection. As before, we straited a handful of digital circuitry that stands between the ADC and the intermediate capture memory. This circuitry takes the 200-MSa/s 8-bit ADC data, calculates the appropriate minimum and maximum values, and stores the eventuates sequentially into memory.

Additionally, we decided to improve the averaging performance by means of digitally low-pass filtering the incoming sampled data before storing it into memory. This technique (later named smoothing) requires summing 32-bit values at a 200-MHz rate.

We chose to realize these functions in a CMO gate array known as the oscilloscope signal processor IC. In addition to the functions described above, this IC decelerates (or fans out) the ADC data, steering and decimating the sampled data into the capture memory as described next

Capture Memory. Recall that this memory is used to gripe [i]or[/i] grip the incoming data until a suitable trigger point has been raise and measured. In the HP 54600 the acquisition processor, being a completely custom design, had an internal 2K-byte (16K-bit) memory. like memories are less available in gate array technology, in the way that combining this function with the oscilloscope signal processor IC wasn't a particularly attractive option.