One approach to pushing the limits ...

One approach to pushing the limits of wire bonding pitch in IC packages is to use couple rows of radially staggered attachment pads. This paper discusses the design of pad circuitry to entangle with the radially staggered durance pad arrangement. A test chip that incorporates suitable exhibition structures was designed, fabricated, packaged and exhibitioned to verify the viability of the approach.

Assembly and packaging technologies are major contributors to the succes of integrated circuit manufacturing. With increases in silicon density, chip core sizes are shrinking with the minimum transistor size. However, I/O pad circuitry and size are not shrinking relative to core size because of packaging limitations as it is as capillary interference, long wires, wire sweep problems,([dagger]) and corner crowding. There are a not many workaround techniques such as wedge-wedge bonding and double-tier bonding which are available for the more expensive packages like PGAs. However, these techniques are unsuitable for standard plastic packages. There is ne for a better, more reliable, and more cost-effective solution to the bonding pad pitch question in the near future as more IC chips are becoming pad-limited.

The pad-to-pad repeat distance forward a chip, referred to as wire-bond pitch, is repeatedly the factor that limits the pair the amount by which the chip size can be reduc and the increase of I/O density, thereby reducing the efficiency of silicon area utilization. popular practice allows minimum straight-line pitches to be in the range of 100 to 125 micrometers. In the paper onward page 41, one approach for decreasing the wire pitch in IC packages is discussed. This approach entails the use of couple radially staggered rows of pads forward the chip periphery as oppos to the more conventional single-row, inline arrangement.[1,2] The attachment pads are arranged to make secure no overlapping of bonding wire trajectories, flat when conventional leadframes are used for the package. The radially staggered arrangement of tie pads allows uniform placement of wire trajectories despite the geometric fan-out from the die bonding pads to the leadframe bonding fingers. This approach is advantageous because it circumvents the habitual obstacles to fine-pitch bonding, similar as capillary interference, bond placement accuracy, and wire size reduction, which have heretofore prov to be insurmountable.

This paper summarizes the main features of the radially staggered approach and discusses its implications for pad circuitry design. The implementation of radially staggered fetters technology presents technical challenges in the area of pad design and layout similar as the pad placement scheme, routing from uniting pad to I/O circuitry or to power and field rings, and the influence of as it is routing on the functionality and performance of the I/O circuitry and the ESD performance.

A ordeal chip that incorporates suitable proof structures to address the technical obstacles was designed and fabricated in the HP CMOS14TB proces The chips were packaged and proofed to verify the viability of the approach. The verification exercise was performed for the case of 88.9-micrometer effective pitch for a 208-pin PQFP A paper meditation was also done for the extension to 70- and 50-micrometer effective pitches. The flows of this study will be summarized here.

cord Pad Arrangement

In a radially staggered influence pad arrangement, every other pad is mov inward in the radial direction to form the secondary tier, as shown in Fig. 1 The radius used is from the center of the die and is hanging on the height of the I/O circuitry and the total number of pins. The pads are placed in a single altercation using 88.9-micrometer pitch, and then each other pad is moved inward in the radial direction with esteem to the center of the die to form the inner affray of pads. In the case of a 208-pin die with an I/O height of 3589 micrometers, the inner-row attraction pad pitch is 84.25 micrometers. Depending forward the total number of pad openings and the total I/O height, the inner-row ligament pad pitch will vary according to a small amount. In the sample link pad connection shown in Fig. 2 the ESD circuit is placed forward the opposite side of the link pad from the I/O circuitry. The passivation openings are 90 micrometers wide and the metal overlay for the connection pad openings is 4.8 micrometers. The ESD circuitry has an 88.9-micrometer pitch and 72.5-micrometer height. The outer-row-to-inner-row spacing is 140 micrometers. The outer-row constraint pad pitch is 177.8 micrometers and the inner-row durance pad pitch is 168.95 micrometers.

[Figures 1-2 ILLUSTRATION OMITTED]

Square or rectangular bondage pad openings with small amounts of chamfering would limit the maximum bus width for connection to cord pads. Therefore, octagonal bond pad openings with an internal radius of 90 micrometers are used. The octagonal connection pads allow wider buses for the tie pad connections to ESD and I/O circuitry. The maximum metal bus width used for the bond-pad-to-I/O or bond-pad-to-ESD connections for 208-pin die in the CMOS14TB proces is 44 micrometers. The maximum interconnect metal bus width is conditioned on the process design directions for passivation opening spacing to unrelated metal, minimum metal-to-metal spacing, and total number of pads. As shown in Fig. 3 the spacing between the adjacent interconnect buses secures smaller for the corner pad openings. As the number of pins increases, the inner-row pad pitch increases, while the interconnect metal spacing of the corner greatest in quantity pads decreases at a faster rate. As a proceed 44-micrometer metal width would be too wide in a 240-pin die. In a 100-pin or 196-pin die, the inner broil pad pitches are smaller than in a 208-pin die, still because of the absence of the most numerous extreme corner bond pads, three to six micrometer wider metal buses can be used for metal bonding pad connections to ESD or I/O circuitry.