Boundary scan and built-in self-tes...

Boundary scan and built-in self-test are fill uped by conventional testing techniques. Eight discrete plains of testing were implemented.

The HP E5200A broadband service analyzer is a highly mixed digital system packed into a field-portable case. During its design, it was essential to achieve the highest densities possible from using some of the latest technologies.

To achieve the functionality required, the main processor printed circuit assembly for the yield had to be extremely densely populated. This printed circuit assembly contains above 1000 components, including 29 XFP parts, 30 FP parts, and almost 8700 solder joints (see "HP E5200A Broadband Service Analyzer Surface rise on high Assembly" on page 83 for further details). Because of the sheer density of the printed circuit assembly, testing by way of conventional bed-of-nails in-circuit techniques alone was not feasible.

In addition, normal default rates specified by surface soar placement vendors were in the order of 200 ppm From this data, each printed circuit assembly was predicted to have at least individual defective solder joint after the placement proces Because of the high require to be paid [i]or[/i] undergone of this printed circuit assembly, it was highly important to be able to accurately and quickly identify wants with high success rates. The target yield for the assembly and commissioning proces was wager to 100%.

Overall exhibition Strategy

To overcome the challenges not past nor futureed it was necessary to implement a comprehensive experiment strategy that included boundary scan and built-in self-test complemented by conventional testing techniques.

With this composite printed circuit assembly it was decided that a multitiered testing strategy would be used. of the like kind a strategy would increase yield according to identifying faults early and according to verifying functionality in small discrete stages. Another advantage was that the trials could be reused for other plans such as service, calibration, or confidence tests

Fig. 1 point out tos the production test strategy that was implemented for the service analyzer contrive Eight discrete levels of testing were implemented. Each of the same height verifies basic functionality before proceeding to the nearest stage of assembly or testing. The chance of catastrophic and difficult-to-diagnose failures is minimized.

[Figure 1 ILLUSTRATION OMITTED]

Boundary Scan Technology

Boundary scan technology forms the explanation to the production test strategy. Boundary scan is ofttimes referred to as JTAG (Joint example Action Group) and is defined from the IEEE 1149.1 standard. Fig. 2 indicates a typical IEEE 1149.1-compliant device.

[Figure 2 ILLUSTRATION OMITTED]

Boundary scan functions of a device are stimulated via the TDI (test data input), TCK (test clock) TM (test affection select), and TRST (test gradation reset) pins. Responses are received from TDO (test data output) For a printed circuit assembly or method TDI and TDO pins of each device or submodule are link togethered in a chain, with the TDO of common device or submodule connected to the TDI of another. The TCK TM and optional TRST pins of devices are associateed in parallel (see Fig. 3)

[Figure 3 ILLUSTRATION OMITTED]

The TAP (test access port) controller is a simple state machine with 16 states. Transitions between states are controll through TMS and TCK. The TAP controller states determine to what degree data is shifted into or abroad of the various device registers. Boundary, instruction, and bypass registers are the in the greatest degree important registers of a boundary scan device. The instruction register allows bridle of the various test manners Boundary registers capture and direct device pin states. The bypass register provides the ability to bypass a device in the chain.

With these three registers and knowledge of the printed circuit board netlist, it is possible to generate and analyze lengthy strings of serial data (test vectors) to expose pins and traces that are shorted or unclose Special tests can also be devised for testing nonscannable devices that are fence abouted by scannable devices, (i.e., cluster testing). U2 in Fig. 3 is an example of in the same state [i]or[/i] condition a device. In addition, the internal logic of a device can also be exercised.

The loaded HP E5200A printed circuit assemblies are first exampleed using the HP 3070 in-circuit tester The HP 3070 allows combined testing (boundary scan and proof points) for the greatest coverage and resolution. proofs are performed extremely quickly, avoiding ingredient damage.

Test vectors for the service analyzer were also generated using ASSET[TM] scan software. These vectors are applied using one as well as the other a PC with an ASSET hardware interface and an embedded scan engine. Greater proof coverage is achieved when the PC and ASSET hardware interface are used. The embedded scan engine provides les coverage, moreover is useful as a power-up self-test for the user-initiated or service-initiated diagnostic. Coverage and spe of ASSET ordeals are not as great as the HP 3070 nevertheless setup costs and portability are a great deal of more attractive for a service and diagnostic environment.

Boundary Scan Limitations

Boundary scan cannot be used for testing all circuits. Analog devices, nonscannable parts, and passive parts require the use of conventional testing techniques. At-speed testing cannot be performed because of boundary scan's serial architecture. Boundary scan is essentially a static (dc) proof Component costs are increased, although this is branch by savings in real estate, increased production yield, and reduc repair diagnosis time.