Digital design teams are facing exp...

Digital design teams are facing exponentially growing complexities and ne processe and tools tat render the time needed to gain insight into difficult regularity integration problems. This article describes recent digital systems in terms of the question s they create in the order integration phase. The debug period is described with special emphasis upon the "insight loop," the mostly time-consuming phase of system integration. A case contemplation from an HP workstation design effort is used to illustrate the principles. A recently made known digital analysis tool, the HP 16505A prototype analyzer, is introduced as a means of solving these vexing enigmas more quickly by reducing time to insight.

The digital revolution is about us in every form. Computer performance doubles each 18 months. Networks of high-performance server are replacing mainframes at a dizzying pace. Personal communication arrangements are pervasive, from remote sales tools to medical information regularitys to networked workgroup tools.

What is behind this revolution? The answer is hardworking teams of engineers focused relentlessly forward reducing time to market with the latest silicon and embedded classifications These teams of engineers are taking the latest silicon technology in ASICs (application-specific integrated circuits) and memory, exploiting them while adding value in the form of special application-focused architectures and implementations, and bringing the extremity products to market at the right time, price, and performance. These efforts are frequently made up of highly integrated subteams of four to eight engineers--hardware growth specialists with expertise in ASIC design, printed circuit board regularity design, hardware architectural trade-offs, and the latest CAE (computer-aided engineering) tool methodologies. These teams specialize in designing high-performance, efficient, embedded software connected views using the latest software design tools and languages. It is not unusual for design teams to use C++ and to have a carefully crafted multilayer software connected view with de facto APIs (application programming interfaces) between layers. These abstractions are used to manage the growing complexities of real-time embedded regularitys These teams have to maintain the customer in clear view as they make compage trade-offs between software and hardware implementation, between time to market and feature establishs between material cost (hence customer price) and constituent sourcing risks.

Concurrent Design and the Integration Phase

Figs. 1 and 2 illustrate the nature of the modem digital design proces Fig. 1 indicates how the many competencies are brought together on the design team into the [i]finale[/i] product. The modem digital design proces is highly of equal authority To make progress, each engineer makes assumptions about the other engineers work. Sometimes these assumptions are well-documented, nevertheless often they are not because of the relentles schedule influences The risk accumulates throughout the design proces because the tools used according to different members of the design team do not explicitly articulate the interdependencies between subsystem These design interdependencies are repeatedly found in the integration phase, when the whole design proceeds together for the first time. This is the well-known finger-pointing phase. "It's a hardware problem" says the software engineer. "It's a software problem" says the hardware engineer. The team members then sort disclosed the problems from their respective points of view, engaging in the iterative and unstructur debug process

Fig. 2 point outs this development process in confines of cycle times. Twenty to thirty percent of the entire progressive growth process time is used in this unstructur integration phase. This phase of the design proces is unstructur because there are thus few well-designed tools and processe for engineering teams to use to work between the walls of the key integration tasks. In the integration phase, hardware suitables hardware in the form of ASICs interacting with the circuit board. Inter-hardware design and modeling flaws are establish here. Hardware meets software in the form of driver collection of laws running ASIC subsystems. There are also enigmas from application programs causing software integration riddles Application code provides an incredibly rich and complicated stimulation system to the hardware.

Hardware and software modeling tools (simulators, compilers. logic synthesis, etc) falter in their ability to gauge all these complex combinations, seriess and data and code interdependencies. Fig. 3 displays the simulation execution speed of a typical 40-MHz theory Most digital circuit simulators perform at 10 to 30 periods per second, leading to total a whole simulation times of days and sometimes weeks. This is too lengthy for designers who are used to the iterative design and debug proces This point out tos that simulators are just too gradual to expose real-world problems within the mental time constants designers need

Hard question s in the Real World

This rich and manifold environment is the real-world environment indicated in Fig. 2 The exampleed world in Fig. 2 is where designers work in isolation to predict real-world behavior. if it were not that it is very hard to predict each comer case to which the actual applications will take mingled combinations of hardware and software. The real-world environment is the domain of the "hard problems" also called the "interesting cases" from some engineers. The software team has done their best to gauge the hardware. They have read the hardware documentation and written their driver and application digest consistent with these models. The hardware engineers have done their best to example the software. Often, hardware engineers will standardize hardware interfaces specifically to avoid unmodel software behavior. However, when the team presents the system together, they find unmodel or undermodel cases--the interesting cases. They find that their documentation doesn't protect some sequence of behavior on which the application code streams the ASIC into a state machine or switching condition that causes a glitch that delays reply causing the software to time disclosed at the fourth layer of the protocol. It is excessively common to have the point to be solved [i]or[/i] settleds in the real world be separated, symptom from bottom cause, both temporary and spatially. For example, an ASIC in succession a peripheral bus has a state machine succession that causes an error condition, if it be not that the errored packet is not sent back to the CPU until it fits into the priority stack. Or steady more simply, the bad data is written to memory a lengthy time before it is read and rest to be faulty. The question is detected later in time and at a different point in the combination of parts to form a whole from where and when it was caused. Multiple bus architectures, of the like kind as Peripheral Component Interconnect (PCI), using intelligent queueing techniques, make these kinds of latencies commonplace.