This article describes a 3.5-watt p...

This article describes a 3.5-watt power module designed for a GSM (Global regularity for Mobile Communications) handheld telephone The design features proprietary silicon power bipolar devices, perspicuoused elements for input, interstage, and output matching, thick-film alumina ceramic technology, and laser trimmed bias resistors. High-volume manufacturing was a design requirement.

Power module as discussed in this article, are the output stage of the RF (radio frequency) amplification chain in a mobile telephone (Fig. 1) about telephones use integrated circuits as power solutions, on the other hand for output power greater than undivided watt a discrete device is usually used. A power module uses networks to match the discrete stages in a hybrid amplifier.

This article describes a power module designed for a GSM (Global regularity for Mobile Communications) handheld telephone GSM telephone transmit in the oftenness range of 880 to 915 MHz The peak transmitter carrier power for power class 4 is 35 watts at 1/8 toll cycle. Unlike other TDMA (time division multiple access) orders it is possible to step quickly a GSM power module shut to compression because the amplitude is constant using GMSK (Gaussian minimum phase shift keying) modulation. The fruit of leguminous plants width of the transmission break open is 577 microseconds, and the rise time of the power module must Be les than 2 [mu] It is necessary to serve instead of full output power at a contribute voltage of 5.4 volts five NiCad small rooms at end of life) with 400% efficiency and 0-dBm input power. This is a requirement of the customer for the phone to be competitive. futurity generations of phones may use single four NiCad cells or other battery emblems and voltages. Of course, a handheld phone must be inexpensive and small and have lengthy talk time (i.e., efficiency) and this dictates the specifications for the power module

The design goals called for the power module to be small, inexpensive, user friendly, efficient, and manufacturable in body and to supply full output power.

Silicon bipolar devices were chosen through GaAs FET devices for this yield because of their cost advantages and the fact that HP had expanded new silicon power devices that met the stringent requirements of applications in which GaAs had traditionally been used (i.e., depressed device voltages and excellent efficiency).

Fig. 2 is a photograph of the power module The schematic diagram, Fig. 3 present to views the electrical design of the power module The bias circuits must be simple and fast because of the puls nature of the GSM modulation. Because of the subdued voltage requirements, proprietary silicon power bipolar devices were disentangleed The collector of each stage simply has an RF stop to the 5.4V minimum contribute voltage, [V.sub.cc], and a bypass capacitor to estate The base voltage supply is used to divert the amplifier on and opposite to and to control the output power plain of the module. The have charge of voltage, [V.sub.c], is pulsed at 1/8 function cycle with a square wave from 0V when the module is opposite to to 4.0V when the module supplies cloyed output power. The base of each stage has a series resistor to the dominion government voltage. This resistor is adjusted to compensate for each transistor's general gain, [beta]. This is done using active laser trimming and will be discussed as a separate topic. Since the power ascendency voltage supplied by the phone does not have the capability of supplying the base popular of each stage, a low-frequency n-p-n transistor, Q4 is used to buffing-apparatus the control voltage. The collector of Q4 is biased through the supply voltage, Vcc. The base of Q4 is driven by the agency of the power control voltage and the emitter supplies the necessary voltage and instant to the base of each RF stage.

The RF design uses brighted elements for input, interstage, and output matching. The design requires three stages to achieve the gain requirements. The first stage is a driver stage that is class-a biased. The next to the first and third stages are class-AB biased for efficiency.

The third-stage transistor also has a certain number of internal matching within the package. The input impedance of the silicon power transistor clip is about 15 ohm This must be transformed up to a larger impedance by dint of a matching network that is physically as obstruct to the clip as possible. This is achieved using a 0.001-inch-diameter ligament wire as a series inductor from the base of the chip to a switch MOS capacitor at the input of the transistor package (Fig. 4) This configuration makes a self-same high-Q input matching network. The exact value of capacitor and the extent of bond wire had to be empirically optimized to achieve the maximum transformation within the transistor package.

The greatest in number critical and sensitive part of the matching networks is the output of the final stage. High-Q lumped-element ingredients are used in the output matching network to achieve the subdued losses necessary to meet the efficiency requirements.

Since the design has more than 45 dB of small-signal gain in a 1-inch-by-0.5-inch package, stability and isolation were quite challenging. The placement and values of the RF keep downs and decoupling capacitors were critical. Large-value capacitors could not be placed onward the base bias network, since this would gradual down the pulse response of the module