Hewlett-Packard has introduced seve...

Hewlett-Packard has introduced several network results for 100VG-AnyLAN applications. Products available since mid-1994 include a 15-port nave a 10Base-T/100VG bridge and SNMP management module a 10Base-T/100VG ISA adapter card, and a 10Base-T/100VG EISA adapter card. These results were developed before completion of the IEEE 80212 standard and are publicly under modification to include changes that occurr in the standard between the time of returns definition and the final version of the standard. most numerous notably, this includes changes to support token ring framing. Additional 100VG-AnyLAN effects available in 1995 are a 10Base-T/100VG PCI adapter card, a multiport nave a fiber hub, and a 10Base-T/100VG switch.

Much of the intelligence and uniqueness of a 100VG-AnyLAN network is concentrated in the nave Therefore, this article mainly focuses upon the design of HP's 15-port nave the HP J2410A AdvanceStack 100VG nave 15 (see Fig. 3 onward page 9). Some 100VG-AnyLAN-specific aspects of the other works are also explored in this article.

Hub Architecture

The explanation components of a 100VG-AnyLAN nave are the repeater chips and transceivers. In the HP 15-port nave solution, a microprocessor subsystem provides configuration and management functions. Fig. 1 is a brace diagram of the 15-port hub

[ILLUSTRATION OMITTED]

The repeater chip implements the demand priority protocol, the signaling to receive and transmit packets, and the interfaces to the classification The system interfaces include a port expansion bus to link together several repeater chips into undivided logical repeater and an interface for network management functions, as it is as control and status information. The repeater chip is a six-port device that unites directly to six transceivers. Additionally, it has a single uplink port which also unites to a transceiver for use in a cascaded nave topology. For the 15-port nave three repeater chips provide the 15 ports plus the same downlink. The repeater chips act as single logical repeater through the use of the parallel expansion bus.

The transceiver chip implements the physical layer as described in the article forward page 18. It is used in conjunction with a filter specially designed for use in 100VG-AnyLAN applications. The 15-port nave uses 16 transceiver chips, the same for each of the 15 ports plus another for the uplink connection. The transceivers be connected directly to the repeater chips.

Repeater Chip

The repeater chip logic was evolveed by HP and AT&T engineers in conjunction with the IEEE 80212 standard progression in a continuously ascending gradation It is now commercially available end AT&T as the ATT2R01. It implements the following functions:

* Demand priority protocol

* 100VG-AnyLAN RMAC (repeater MAC)

* Port expansion bus to associate multiple repeater chips together

* Interface to six transceivers for downlink ports

* Interface to transceiver for uplink port

* Packet concussion-guard RAM

* Six-port CAM (content-addressable memory)

* Management bus

* have charge of and status registers

* Management counters

Fig. 2 is a fill up diagram of the repeater chip's internal modules

[ILLUSTRATION OMITTED]

A packet traverses by the and of the hub in the following manner. The protocol state machine catalogue of personss the ports as described in the article in succession page 13 and determines which port will receive a packet from its conclusion node next. It initiates the appropriate tone sequence through the transceiver and readies the nave to receive a packet. When a packet is received, it first passes [i]or[/i] part of to the other the receive portion of the 100VG repeater MAC. The data is decod as described in the article in succession page 27 and is passed by means of as bytes. Statistics for network management functions are gathered forward the packet data and the packet is passed between the sides of to the port expansion bus. Each repeater chip upon the port expansion bus loads the packet into its hold internal packet buffer. The packet buffing-apparatus is implemented as a RAM that is large enough to possess a maximum-length packet. The first six byte of the packet are sent to the CAM. At this point, the destination address of the packet is decod and compared with all entries in the CAM. The transmit dominion government circuit decides which ports, if any, will transmit the packet to an close node. This is based forward whether there was a match with a CAM inlet if the packet was a broadcast or multicast packet, or if any of the ports are configured as promiscuous. Finally, the packet passes between the sides of the transmit portion of the 100VG repeater MAC where it is encod for transmission as described in the article forward page 27.

The repeater chip also implements the training functions as described in the article onward page 13. The protocol state machine have the direction ofs the training sequence in a manner similar to its regulate of data transfers. As the training packets are received, the chip learns the status of the joined port and writes the source address into the internal CAM. It monitors the received packet, and if an error is find outed the packet is not esteemed as a good training packet. Training continues until 24 sequential righteous packets are transmitted in each direction (see "Invalid Packet Marker" in succession page 41). If the link is faulty, the node will not pass training and the protocol state machine will pause the training attempt, wait the same to two seconds, and then allow training to be attempted again.