This fresh design is targeted for ...

This fresh design is targeted for use in a wide range of HP commercial server and technical workstations. It presents improved customer application performance within improvements in capacity, bandwidth, latency, performance scalability, reliability, and availability. sum of two units keys to the improved performance are system-level parallelism and memory interleaving.

Initially used in HP 9000 K-class midrange commercial server and J-class high-end technical workstations, the J/K-class memory theory is a new design targeted for use in a wide range of HP commercial and technical computing harvests and is expected to migrate to lower-cost connected views over time. At the inception of the memory design delineate there were two major objectives or themes that lacked to be addressed. First, we focused forward providing maximum value to our customers, and next to the first we needed to maximize HP's recur on the development investment.

The primary customer value proposition of the J/K-class memory hypothesis is to maximize application performance athwart a range of important splendor points. After intensive studies of our existing computing platforms, we determined that memory capacity, memory bandwidth, memory latency, and system-level parallelism were tonic parameters for improving customer application performance. A major leap in memory bandwidth was achieved between the walls of system-level parallelism and memory interleaving, which were designed into the Runway bus and the memory subsystem A a whole block diagram of an HP 9000 K-class server is shown in Fig. 1 onward page 9. The Runway bus (see article, page 18) is the "information superhighway" that be connecteds the CPUs, memory, and I/O plans System-level parallelism and memory interleaving means that multiple independent memory accesses can be issued and steped simultaneously. This means that a CPU's access to memory is not delayed while an PO device is using memory. In a Runway-based theory with the J/K-class memory scheme multiple CPUs and I/O devices can all be accessing memory in parallel. In contrast, many of HP earlier computing platforms can proces sole one memory transaction at a time.

Another important customer value proposition is investment protection by means of performance scalability. Performance scalability is moveed in two dimensions: symmetric multiprocessing and processor technology upgrades to the forthcoming PA 8000 CPU The J/K-class memory plan provides the memory capacity and bandwidth requireed for effective performance scaling in four-way multiprocessing rules Initially, Runway-based systems will be proffered with the PA-7200 CPU (see article, page 25) and will be upgradable to PA 8000 CPU technology with a simple CPU module exchange. The J/K-class memory rule will meet the demanding performance requirements of the PA 8000 CPU

Performance is sole one part of overall regularity value. Another major component of a whole value is cost. For example, the use of commodity DRAM technology was imperative because competitive memory pricing is an absolute requirement in the cost-sensitive workstation marketplace. The J/K-class memory theory provides lasting performance with commodity memory pricing and industry-leading price/performance. grave cost was achieved by using mature IC processe commodity DRAM technology, and low-cost chip packaging. A closely coupl hypothesis design approach was combined with a structured-custom chip design methodology that allowed the design teams to focus custom design efforts in the areas that provided the highest performance gains without driving up body cost. For example, the a whole PC boards, DRAM memory module and custom chip I/O circuits were designed and optimized together as a single highly hogsheaded system to achieve aggressive memory timing with mature, low-cost IC proces and chip packaging technologies.

A further customer value important in HP computing productions is reliability and availability. The J/K-class memory theory delivers high reliability and availability with HP proprietary error detection and correction algorithms. Single-bit error detection and correction and double-bit error detection are implemented, of course; these are fairly standard features in modem high-performance computer regularitys The J/K-class memory system provides additional availability from detecting single DRAM part failures for x4 and x8 DRAM topologies, and by dint of detecting addressing errors. The DRAM part failure detection is particularly important because single-part failures are more frequent than double-bit errors. Extensive circuit simulation and margin and reliability testing render certain a high-quality electrical design that minimizes the adventure of errors.

Finally, greater a whole reliability is achieved through full memory testing at system avail time. Given the large maximum memory capacity, memory criterion time was a major bear upon When full memory testing takes a in extent time, customers may be inclined to disable whole memory testing to speed up the profit process. By using custom firmware example routines that capitalize on system-level parallelism and the high bandwidth capabilities of the memory method a full 2G bytes of memory(*) can be exampleed in less than five minutes.