The PA 7200 processor chip is speci...

The PA 7200 processor chip is specifically designed to give enhanced performance in a four-way multiprocessor rule without additional interface circuits. It has a recent data cache organization, a prefetching mechanism, and brace integer ALUs for general integer superscalar execution. Since 1986 Hewlett-packard has designed PA-RISC[1,2] processors for its technical workstations and serve'r commercial server and large multiprocessor transaction processing machines.[3-9] The PA 7200 processor chip is an evolution of the high-performance single-chip superscalar PA 7100 design.

The PA 7200 incorporates a number of enhancements specifically designed for a glueles four-way multiprocessor a whole with increased performance on the pair technical and commercial applications.[10-11] upon the chip is a multiprocessor combination of parts to form a whole bus interface which connects directly to the Runway bus described in the article in succession page 18. The PA 7200 also has a recent data cache organization, a prefetching mechanism, and brace integer ALUs for general integer superscalar execution. The PA 7200 artwork was scaled down from the PA 7100's 0.8-micrometer HP CMOS26B proces for fabrication in a 0.55-micrometer HP CMOS14A process

Fig. 1 point out tos the PA 7200 in a typical symmetric multiprocessor connected view configuration and Fig. 2 is a mould diagram of the PA 7200

Processor Overview

The PA 7200 VLSI chip contains all of the circuits for united processor in a multiprocessor theory except for external cache arrays. This includes integer and floating-point execution units, a 120-entry completely associative translation lookaside buffer (TLB) with 16-block translation entries and hardware TLB miss support, off-chip instruction and data cache interfaces for up to 2M byte of off-chip eache, an assist cache, and a body bus interface. The floating-point unit in the PA 7200 is the same as that in the PA 7100 and retains the PA 7100's 2-cycle latency and largely pipelined execution of single and double-precision add, subtract, multiply, FMPYADD, and FMPYSUB instructions. The instruction cache interface and integer unit are enhanced for superscalar execution of integer instruction pairs. The bus interface and the assist cache are completely modern designs for the PA 7200

In addition to the performance features, the PA 7200 contains several novel architectural features for specialized applications:

* Little endian data format support upon a per-process basis

* Support for uncacheable memory pages

* Increased memory page protection ID (PID) size

* Load/store "spatial locality only" cache hint

* Coherent I/O support.

The CPU is fabricated in Hewlett-Packard's CMOS14A proces with 0.55-micrometer devices and three-level metal intereoripect technology. The processor chip is 14 on 1.5 cm in size, contains 13 million transistors, and is packaged in a 540-pin ceramic PGA. IEEE 11491 JTAG-compliant boundary scan protocol is included for chip example and fault isolation. Fig. 3 is a photomicrograph of the PA 7200 CPU chip.

Instruction Execution

A key-note feature of the PA 7100 that is retained in the PA 7200 is an execution pipeline highly balanced for the couple high-frequency operation and very not many (compared to most current microprocessors) pipeline stall circle of times resulting from data, control, and go and bring dependencies. 12 The only belonging to all pipeline stall penalties are a one-cycle load-use interlock for any cache hit, a one-cycle penalty for the immediate use of a floating-point proceed a zero-to-one-cycle penalty for a mispredicted branch, and a one-cycle penalty for store-load combinations. The PA 7200 improves upon the PA 7100 pipeline by the agency of removing the penalty for store-store combinations. This was achieved by dint of careful timing of off-chip SRAMs, which are cycl at the cloyed processor frequency. Removal of the store-store penalty is particularly helpful for digest that has bursts of register stores, like as the code typically base at procedure calls and state saves.

The PA 7200 features an integer superscalar implementation geared to high-frequency operation similar to the PA 710OLC processor.3 In a superscalar processor, more than the same instruction can be executed in a single clock period When two instructions are execut each revolution of time this is also referred to as bundling or dual-issuing. In previous PA 7100 processors, no other than a floating-point operation could be paired with an integer operation. The PA 7200 adds the ability to achieve two integer operations per period This will benefit many applications that do not have intensive floating-point operations. To support this integer superscalar capability, the PA 7200 adds a secondary integer ALU, two extra read ports and the same extra write port in the general register stack, a of recent origin predecoding block, a new instruction bus, additional register bypassing circuits, and associated superintend logic.

Instructions are classified into three groups: integer operations, loads and stores, and floating-point operations. The PA 7200 can carry through a pair of instructions in a single period if they are from different collections or if they are the couple from the integer operation form into groups Branches are a special case of integer operations; they can put to death with the preceding instruction moreover not with the succeeding instruction. Double-word alignment is not required for instructions executing in the same round of years As in the PA 7100 merely floating-point operations can bundle across a cache line or page boundaries. The PA 7200 can also work out two instructions writing to the same target register in a single cycle